1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a word-line selecting circuit for selecting and driving a word line.
2. Description of the Related Art
As the integration density of the semiconductor memory increases, it is increasingly demanded that the power-supply voltage VCC of the memory be reduced and that the data be read from the memory faster.
FIG. 1 shows conventional word-line selecting circuits which are identical and incorporated in a semiconductor memory. As illustrated in FIG. 1, each word-line selecting circuit has a P-channel MOS field-effect transistor (PMOSFET) and an N-channel MOS field-effect transistor (NMOSFET). A boosted potential VPP is applied to the source of the PMOSFET. The potential VPP is higher than the power-supply voltage VCC applied to the circuit from an external power supply. The potential VPP is generated by, in most cases, a boosted potential generating circuit (not shown) which is provided in the memory chip. A ground potential VSS is applied to the source of the NMOSFET.
The PMOSFET and the NMOSFET are connected at their drains. The node of the drains of the MOSFETs is connected to one end of a word line WL. Connected to the word line WL are memory cells, only one of which is shown in FIG. 1. The gates of the PMOSFET and the gate of the NMOSFET are connected to each other. The node of the gates is connected by a level-shifting circuit to a row decoder. The power-supply voltage VCC is applied to the row decoder. The row decoder is controlled by control signals such as address signals and precharge signals, to generate an output signal S.sub.VCC which is a VCC-based signal. The level-shifting circuit changes the level of the output signal to generate a VPP-based signal S.sub.VPP whose high level is equal to the VPP level. The signal S.sub.VPP is supplied to the gate of the PMOSFET and to the gate of the NMOSFET.
In the word-line selecting circuit of in FIG. 1, the PMOSFET is provided between the word line WL and the boosted potential VPP terminal in order to drive the word line WL. The PMOSFET is used in place of a boot-strap circuit which is incorporated in the ordinary word-line selecting circuit. The boot-strap circuit is comprised of an NMOSFET for driving a word line and an isolation transistor, in order to lower the power-supply voltage and shorten the time for selecting a word line.
With the word-line selecting circuit of in FIG. 1, wherein the PMOSFET is used in place of a boot-strap circuit, it is required that the control signal supplied to its gate be a VPP-based signal whose high level is equal to the VPP level. This is because the PMOSFET would not be turned off completely by a VCC-based signal at its high level (i.e., the VCC level) since the source voltage of the PMOSFET is set at the boosted potential VPP. Although the PMOSFET must be controlled by a VPP-based signal, the output signal of the row decoder is a VCC-based one. It is therefore necessary to convert the VCC-based signal to a VPP-based signal. This is why the level-shifting circuit is indispensable to the word-line selecting circuit shown in FIG. 1.
A memory device of this type is disclosed in, for example, U.S. Pat. No. 4,344,005.
U.S. Pat. No. 4,344,005 also discloses a word-line killer circuit as well as a level-shifting circuit. The word-line killer circuit sets a word line at the ground potential when a boosted potential VPP is applied to another word line. The word-line killer circuit is driven by a killer-driving circuit. Like the level-shifting circuit, the killer-driving circuit uses the boosted potential VPP as power-supply voltage.
FIG. 2 shows another conventional word-line selecting circuit. This circuit includes two PMOSFETs (shown in the broken-line box LS) which correspond to the level-shifting circuit used in the circuit of FIG. 1. The PMOSFETs are incorporated in the row decoder section for one word line and have their gates cross-connected.
A memory device of this type is disclosed in, for example, IEEE Journal of Solid-State Circuits, Vol. 26, No. 8, August 1991, pp. 1171-1175.
Jpn. Pat. Appln. KOKAI Publication No. 4-106794 discloses an EPROM. In the EPROM, address signals are level-shifted before they are input to a row decoder.
The use of the two types of the conventional word-line selecting circuits, both described above, is disadvantageous in the following respects.
The memory devices shown in FIGS. 1 and 2 need to have a number of level-shifting circuits. This is because each word-line selecting circuit must be provided with one level-shifting circuit. More precisely, exactly as many level-shifting circuits as the word lines are required in the memory devices of FIGS. 1 and 2.
Similarly, a memory device wherein address signals are level-shifted before they are input to a row decoder must have a number of level-shifting circuits. This is because one level-shifting circuit needs to be provided for each address-signal line.
The greater the number of level-shifting circuits provided, the larger the chip size. Further, the larger the number of level-shifting circuits, the greater the consumption of power used to generate the boosted potential VPP. This is because each level-shifting circuit uses the boosted potential VPP as power-supply voltage.
The consumption of power used to generate the boosted potential VPP increases also when circuits using the boosted potential VPP as power-supply voltage are provided in chip in large numbers.
As the consumption of power used to generate the potential VPP increases, the boosted potential VPP is more likely to vary. In particular, a low boosted potential VPP tends to lower. To suppress the the variation of the potential VPP, a sufficiently high potential must be applied to vary the boosted potential line. In order to apply such a potential to the boosted potential line, the capacitor incorporated in the boosted-potential generating circuit needs to have a large area. The larger the area of the capacitor, the larger the chip size.
Third, the level-shifting circuit may cause errors since it must be located adjacent to the memory-cell region due to the chip-layout and is inevitably influenced by the noise generated in the memory-cell array. The higher the integration density of the memory, the greater the influence the noise imposes on the level-shifting circuit. The word-line selecting circuit is very likely to cause errors if incorporated in a 64-MB or 256-MB dynamic RAM.